Low Power VLSI CMOS Design An Image Processing Chip for RGB to HSI Conversion

Up until recently performance parameters such as area and speed were the important key factors in the design of integrated circuits. With the introduction of smaller technologies these objectives were more easily achieved. However, increasing integration and higher clock speeds has moved power dissipation to the forefront of design challenges facing today's chip designers. By implementing low power structures from the first stages of the design cycle expensive cooling techniques and packaging can be avoided, even when implementing fast real time image processing algorithms. Most research towards low power design has been done at the lower levels of the disign hierarchy. However, the field of high level or architectural level low power design is likely to be of increasing significance. The aim of this project is to demonstrate that the use of low power strategies at the initial stages of the design development cycle will lead to a significantly reduced power consumption in the final chip.